1. Field of the Invention
This invention relates to the field of switches, and particularly to switches having programmable transfer rates.
2. Description of the Related Art
A conventional active matrix liquid crystal display (LCD) device will be briefly described with reference to FIG. 1a, which shows a typical equivalent circuit diagram showing an area including one pixel. Each pixel 2 is located at an intersection between a gate line X and a signal line Y. The pixel is comprised of a liquid crystal material and has an equivalent capacitance CLC. The liquid crystal capacitance is connected to a driver transistor TFT1 at one end, and to a reference voltage Vcom at its other end. TFT1 typically comprises a MISFET-type thin film transistor (TFT). The drain of TFT1 is connected to signal line Y to receive a video signal Vsig, and TFT1's source is connected to CLC; i.e., the pixel electrode. The gate of TFT1 is connected to gate line X.
In operation, a pulse with a voltage Vgate is applied to the gate of TFT1, which turns on and connects Vsig to pixel 2 to charge CLC. Ideally, Vsig is maintained by CLC and the pixel excitation remains constant after the termination of the gate pulse. However, a coupling capacitance CGS is present between pixel 2 and the gate of TFT1. Coupling capacitance CGS is a combination of a floating capacitance component between the pixel electrode and the gate line X, and a parasitic capacitance component between the source area and a gate area within TFT1. The parasitic capacitance component is predominant, and tends to vary from one TFT to another.
When the drive pulse goes positive to turn on TFT1, the charge on CGS is coupled to CLC, which results in a positive voltage shift +ΔV in Vsig as applied to pixel 2. However, with TFT1 on, the charge delivered by CGS is bled off to the low-impedance amplifier (not shown) driving column line Y via TFT1, such that the positive shift subsides quickly.
However, when the drive pulse falls, pixel capacitance CLC is coupled to CGS and CLC is partially discharged. As illustrated in the timing diagram shown in FIG. 1b, this results in a negative voltage shift −ΔV in Vsig as applied to pixel 2. Here, though, switch TFT1 is off; as such, the coupled charge is not bled off and voltage shift −ΔV is maintained throughout TFT1's off-time.
Since CGS varies from one TFT to another, ΔV will also vary from pixel to pixel. The transmissivity of the pixel is dependent on the effective voltage applied across it; as such, voltage shift ΔV and its variability from pixel to pixel can cause significant deterioration in the quality of the displayed image.
One approach to reducing ΔV requires connecting an auxiliary capacitor CS across pixel 2. This additional capacitance is intended to compensate for the charge lost to coupling capacitor CGS when the gate pulse ends, and thereby reduce the magnitude of ΔV. However, capacitor CS is necessarily formed in the pixel area. As such, the presence of CS may compromise the opening ratio of the pixel and degrade the display's contrast.
Another way to reduce the magnitude of ΔV is to “shape” the falling edge of the gate pulse to smooth its transition from high to low and thereby increase the pulse's fall time. In this way, the switch is at least partially on during the pulse's fall time, which allows at least some of the charge to be bled back to the column amplifier via TFT1. Since this charge is presumably small in comparison with the video signal, most of it can be bled off during the slow fall time, even though the resistance of TFT1 is rising.
One way to shape the gate pulse's falling edge is described in U.S. Pat. No. 5,587,722 to Suzuki et al. Here, gate pulses are provided to each TFT via respective inverters, each of which is made up of an n-type transistor and a p-type transistor, with the p-type transistor having a larger current capacity than the n-type transistor. When the gate pulse transitions from low to high, the p-type transistor is turned on, and a rapid rise time results due to the p-type transistor's larger size. However, when the gate pulse transitions from high to low, the n-type transistor is turned on, and a smooth, slower fall time results due to the n-type transistor's smaller size.
This approach has several drawbacks. The negative slew rate that results from the patented method is strongly dependent on several factors, including the fabrication technology used, process variations, temperature drift, and the supply voltage. In addition, when implemented as shown in FIG. 2 of the patent, the gate pulse can only swing between ground and the supply voltage; no other steady-state voltages are possible.